Fan-Out Packaging
Fan-Out packaging continues to gain prominence within the industry, based on significant technical advantages that have led to its broad commercialization. As we move further into the era of system-in-package (SIP) and heterogeneous integration, Fan-Out packaging will become increasingly significant. ASE is evolving this advanced packaging platform to meet application demands for smaller form factors and improved electrical and thermal performance.
What is Fan-Out Packaging?
Literally speaking, “Fan-Out” packaging can be defined as any package with connections fanned-out of the chip surface, enabling more external I/Os. Conventional fan-out packages use an epoxy mold compound to fully embed the dies, rather than placing them upon a substrate or interposer. Fan-Out packaging typically involves dicing chips on a silicon wafer, and then very precisely positioning the known-good chips on a thin “reconstituted” or carrier wafer/panel, which is then molded and followed by a redistribution layer (RDL) atop the molded area (chip and fan-out area), and then forming solder balls on top.
A popular packaging technique now is to build packages with a standard Fan-Out type RDL, but with dies embedded in materials such as organic laminate or silicon wafer instead of the mold compound. Please refer to “ ” for more details.
Fan-Out is a wafer-level packaging (WLP) technology. It is essentially a true chip-scale packaging (CSP) technology since the resulting package is roughly the same size as the die itself. When dealing with shrinking pitch design requirements, Fan-In WLP faces processing challenges as the area available for I/O layout is limited to the die surface. Fan-Out WLP, however, does not have this limitation as the technique allows for the redistribution of I/Os beyond the die surface and onto the over-mold which, in turn supports a thinner package.